LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY test_adder IS
END test_adder;
 
ARCHITECTURE behavior OF test_adder IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT add_sub
    PORT(
         ADD_SUB_CONTROL : IN  std_logic;
			is_signed : IN STD_LOGIC;
			is_slt : in STD_LOGIC; -- 1 if this is slt (together with add_sub_control = '1')
         A : IN  std_logic_vector(31 downto 0);
         B : IN  std_logic_vector(31 downto 0);
         result : OUT  std_logic_vector(31 downto 0);
			
			carry_flag : out std_logic;
			overflow_flag : out std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal ADD_SUB_CONTROL : std_logic;
   signal A : std_logic_vector(31 downto 0) := (others => '0');
   signal B : std_logic_vector(31 downto 0) := (others => '0');
	signal is_signed : STD_LOGIC;
	signal is_slt : STD_LOGIC; 
	
 	--Outputs
   signal result : std_logic_vector(31 downto 0);
	signal carry_flag : std_logic;
	signal overflow_flag : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: add_sub PORT MAP (
          ADD_SUB_CONTROL => ADD_SUB_CONTROL,
          A => A,
          B => B,
          result => result,
			 is_slt => is_slt,
			 is_Signed => is_signed,
			 carry_flag => carry_flag,
			 overflow_flag => overflow_flag
        ); 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      -- insert stimulus here 
		
		is_slt <= '0';
		is_signed <= '0';
		-------------------
		-- ADDITION
		--- Ans = 66667777h
		A <= x"11112222";
		B <= x"55555555";
		ADD_SUB_CONTROL <= '0';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		--- Ans = 112340122h
		A <= x"FFFFAAAA";
		B <= x"12345678";
		ADD_SUB_CONTROL <= '0';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		--- Ans = 01010101h;
		A <= x"01010101";
		B <= x"00000000";
		ADD_SUB_CONTROL <= '0';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		--- Ans = 00000000h;
		A <= x"00000000";
		B <= x"00000000";
		ADD_SUB_CONTROL <= '0';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		A <= x"80000000";
		B <= x"80000001";
		ADD_SUB_CONTROL <= '0';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		A <= x"80000000";
		B <= x"FFFFFFFF";
		ADD_SUB_CONTROL <= '0';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		------------------
		-- Subtraction
		------------------
		
		--- Ans = 8ACF1357h;
		A <= x"12345678";
		B <= x"87654321";
		ADD_SUB_CONTROL <= '1';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		--- Ans = 00000000h;
		A <= x"00000000";
		B <= x"00000000";
		ADD_SUB_CONTROL <= '1';
		
		wait for 50 ns;
		is_signed <= '1';
		wait for 50 ns;
		is_signed <= '0';
		
		---------------------
		
		is_slt <= '1';
		is_signed <= '1';
		--- Ans = 00000000h;
		A <= x"80000000";
		B <= x"80000001";
		ADD_SUB_CONTROL <= '1';
		
		wait for 50 ns;
		
      wait;
   end process;

END;
